This invention relates to semiconductor devices. More particularly, it is concerned with methods of making electrical contact to elements of semiconductor devices.
In conventional planar semiconductor device technology the flow of current between the source and drain electrodes of a field effect transistor (FET) is controlled by applying a gate voltage to its gate electrode. The gate voltage increases or decreases the width of the depletion layer of the gate region between the source and the drain, and thus alters the effective resistance of the device. That is, an FET is basically a voltage-controlled resistor. In order to reduce significantly the current passing between the source and the drain, the gate voltage should be able to increase the width of the depletion layer to a dimension comparable to the total width of the current path. Thus, for practical purposes, the current channel of an FET fabricated by conventional planar technology is limited to about 1 to 10 micrometers. These physical limitations of the device elements limit the amount of current which can be controlled.
An improved FET capable of handling larger amounts of current as described and claimed in application Ser. No. 941,478 filed concurrently herewith includes a matrix of semiconductor material having an array of individual rods of conductive material disposed therein. The rods serve as control or gate elements in the FET. In order to provide biasing potential to the rods electrical contacts must be made to the rods without producing short-circuits to the semiconductor matrix.